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PRELIMINARY DATA SHEET
1GB Unbuffered DDR2 SDRAM DIMM
EBE11ED8AGWA (128M words x 72 bits, 2 Ranks)
Specifications
* Density: 1GB * Organization 128M words x 72 bits, 2 ranks * Mounting 18 pieces of 512M bits DDR2 SDRAM sealed in FBGA * Package: 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) * Power supply: VDD = 1.8V 0.1V * Data rate: 667Mbps/533Mbps (max.) * Four internal banks for concurrent operation (components) * Interface: SSTL_18 * Burst lengths (BL): 4, 8 * /CAS Latency (CL): 3, 4, 5 * Precharge: auto precharge option for each burst access * Refresh: auto-refresh, self-refresh * Refresh cycles: 8192 cycles/64ms Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Operating case temperature range TC = 0C to +95C
Features
* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Data mask (DM) for write data * Posted /CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality * /DQS can be disabled for single-ended Data Strobe operation
Document No. E0920E10 (Ver. 1.0) Date Published June 2006 (K) Japan Printed in Japan URL: http://www.elpida.com
Elpida Memory, Inc. 2006
EBE11ED8AGWA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) Contact pad Gold
Part number
Package 240-pin DIMM (lead-free)
Mounted devices EDE5108AGBG-6E-E EDE5108AGBG-6E-E EDE5108AGBG-5E-E
EBE11ED8AGWA-6E-E 667 EBE11ED8AGWA-5C-E 533
Pin Configurations
Front side 1 pin 64 pin 65 pin 120 pin
121 pin Back side
184 pin 185 pin
240 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin name VREF VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS NC NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS /DQS2 DQS2
Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Pin name A4 VDD A2 VDD VSS VSS VDD NC VDD A10/AP BA0 VDD /WE /CAS VDD /CS1 ODT1 VDD VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
Pin name VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS CK1 /CK1 VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS
Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Pin name VDD A3 A1 VDD CK0 /CK0 VDD A0 VDD BA1 VDD /RAS /CS0 VDD ODT0 A13 VDD VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name VSS DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS /DQS8 DQS8 VSS CB2 CB3 VSS VDD CKE0 VDD NC NC VDD A11 A7 VDD A5 Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin name DQ40 DQ41 VSS /DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin name DQ22 DQ23 VSS DQ28 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS VDD CKE1 VDD NC NC VDD A12 A9 VDD A8 A6 Pin No. 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin name DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK2 /CK2 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Pin Description
Pin name A0 to A13 A10 (AP) BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS8, /DQS0 to /DQS8 DM0 to DM8 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 NC Function Address input Row address Column address Auto precharge Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground ODT control No connection A0 to A13 A0 to A9
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation Voltage interface level of this assembly DDR SDRAM cycle time, CL = 5 -6E -5C 10 SDRAM access from clock (tAC) -6E -5C 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width Reserved Bit7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Bit6 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 Bit5 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 Bit4 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 Bit3 0 1 1 1 1 0 1 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 1 1 Bit2 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 Bit1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 Bit0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 Hex value Comments 80H 08H 08H 0EH 0AH 61H 48H 00H 05H 30H 3DH 45H 50H 02H 82H 08H 08H 00H 0CH 04H 38H 01H 02H 00H 03H 3DH 50H 50H 60H 3CH 1EH 128 bytes 256 bytes DDR2 SDRAM 14 10 2 72 0 SSTL 1.8V 3.0ns*
1
3.75ns* 0.45ns* 0.5ns* ECC 7.8s x8 x8 0 4,8 4 3, 4, 5
1
1
1
SDRAM device attributes: 0 Burst length supported SDRAM device attributes: Number of 0 banks on SDRAM device SDRAM device attributes: 0 /CAS latency DIMM Mechanical Characteristics DIMM type information SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CL = 4 -6E, -5C Maximum data access time (tAC) from clock at CL = 4 -6E, -5C Minimum clock cycle time at CL = 3 Maximum data access time (tAC) from clock at CL = 3 Minimum row precharge time (tRP) Minimum row active to row active delay (tRRD) 0 0 0 0 0 0 0 0 0 0
4.00mm max. Unbuffered Normal Weak Driver 50 ODT Support 3.75ns* 0.5ns* 5.0ns* 0.6ns* 15ns 7.5ns
1 1
1
1
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Byte No. 29 30 31 32
Function described
Bit7
Bit6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit5 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0
Bit4 1 0 0 0 0 0 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 0 0 0
Bit3 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 0
Bit2 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0
Bit1 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0
Bit0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Hex value Comments 3CH 2DH 80H 20H 25H 27H 37H 10H 17H 22H 3CH 1EH 1EH 00H 00H 3CH 69H 80H 18H 1EH 22H 28H 00H 00H 15ns 45ns 512M bytes 0.20ns* 0.25ns* 0.27ns* 0.37ns* 0.10ns* 0.17ns* 0.22ns* 15ns*
1 1
Minimum /RAS to /CAS delay (tRCD) 0 Minimum active to precharge time (tRAS) -6E, -5C Module rank density Address and command setup time before clock (tIS) -6E -5C Address and command hold time after clock (tIH) -6E -5C 0 1 0 0 0 0
1
33
1
1
34 35
Data input setup time before clock (tDS) 0 -6E, -5C Data input hold time after clock (tDH) 0 -6E -5C 0 0
1
1
1
36 37 38 39 40 41 42 43 44
Write recovery time (tWR)
Internal write to read command delay (tWTR) 0 -6E, -5C Internal read to precharge command 0 delay (tRTP) Memory analysis probe 0 characteristics Extension of Byte 41 and 42 Active command period (tRC) -6E, -5C Auto refresh to active/ Auto refresh command cycle (tRFC) SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -6E -5C Data hold skew (tQHS) -6E -5C 0 0 0 1 0 0 0 0 0 0
7.5ns* 7.5ns* TBD
1
1
Undefined 60ns*
1
105ns* 8ns*
1
1
0.24ns* 0.30ns* 0.34ns* 0.40ns*
1
1
45
1
1
46 47 to 61
PLL relock time
Undefined
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Byte No. 62 63
Function described SPD Revision Checksum for bytes 0 to 62 -6E -5C
Bit7 0 1 1 0 1 0
Bit6 0 0 1 1 1 0
Bit5 0 0 0 1 1 0
Bit4 1 0 0 1 1 0
Bit3 0 0 1 1 1 0
Bit2 0 1 0 1 1 0
Bit1 1 0 0 1 1 0
Bit0 0 0 0 1 0 0
Hex value Comments 12H 84H C8H 7FH FEH 00H (ASCII-8bit code) Continuation code Elpida Memory Rev. 1.2
64 to 65 66 67 to 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -6E -5C Module part number -6E -5C
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 0 0 0
0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 0 1 1 1
0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 0 1 1 0 0 0
0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0
1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0
45H 42H 45H 31H 31H 45H 44H 38H 41H 47H 57H 41H 2DH 36H 35H 45H 43H 2DH 45H 20H 30H 20H
E B E 1 1 E D 8 A G W A -- 6 5 E C -- E (Space) Initial (Space) Year code (BCD) Week code (BCD)
87
88 89 90 91 92 93 94 95 to 98 99 to 127
Module part number Module part number Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacture specific data
Note 1:
These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Block Diagram
/CS1 /CS0
/DQS0
DQS0
RS1
RS1
/DQS4
DQS4
RS1
RS1
RS1
DM /CS DQS /DQS
DM /CS DQS /DQS
DM0
RS1
DM /CS DQS /DQS
DM /CS DQS /DQS
DM4
8
RS1
DQ0 to DQ7
DQ0 to DQ7
D0
DQ0 to DQ7
D9
DQ32 to DQ39
8
RS1
DQ0 to DQ7
D4
DQ0 to DQ7
D13
/DQS1
RS1
DQS1
RS1
RS1
/DQS5
RS1
DQS5
RS1
RS1
DM /CS DQS /DQS
DM /CS DQS /DQS DQ0 to DQ7
DM1
DM5
DM /CS DQS /DQS
8
RS1
DM /CS DQS /DQS DQ0 to DQ7
DQ8 to DQ15
DQ0 to DQ7
D1
D10
8
RS1
DQ40 to DQ47
DQ0 to DQ7
D5
D14
/DQS2
RS1
/DQS6
RS1
DQS2
RS1
RS1
DM /CS DQS /DQS
DM /CS DQS /DQS DQ0 to DQ7
DQS6
RS1
RS1
DM /CS DQS /DQS
DM /CS DQS /DQS DQ0 to DQ7
DM2
DM6
8
RS1
DQ16 to DQ23
DQ0 to DQ7
D2
D11
8
RS1
DQ48 to DQ55
DQ0 to DQ7
D6
D15
/DQS3
RS1
DQS3
RS1
RS1
DM /CS DQS /DQS
DM /CS DQS /DQS DQ0 to DQ7
/DQS7
RS1
DQS7
RS1
RS1
DM /CS DQS /DQS
DM /CS DQS /DQS DQ0 to DQ7
DM3
DM7
8
RS1
DQ24 to DQ31
DQ0 to DQ7
D3
D12
8
RS1
DQ56 to DQ63
DQ0 to DQ7
D7
D16
BA0 to BA1
A0 to A13 /RAS /CAS /WE
RS2
RS2
RS2
RS2
RS2
/DQS8
BA0 to BA1: SDRAMs (D0 to D17)
A0 to A13: SDRAMs (D0 to D17)
/RAS: SDRAMs (D0 to D17)
/CAS: SDRAMs (D0 to D17)
/WE: SDRAMs (D0 to D17)
RS1
DQS8
RS1
RS1 DM /CS DQS /DQS DM /CS DQS /DQS
DM8
8
RS1
CB0 to CB7
CKE0
CKE1
ODT0 ODT1
VDDSPD VREF
VDD
VSS
CKE: SDRAMs (D0 to D8)
CKE: SDRAMs (D9 to D17)
ODT:SDRAMs (D0 to D8) ODT:SDRAMs (D9 to D17)
DQ0 to DQ7
D8
DQ0 to DQ7
D17
Serial PD
SPD
SDRAMs (D0 to D17)
SDRAMs (D0 to D17)
SDRAMs (D0 to D17)
SCL
SA0
SA1
SA2
SCL
SDA
SDA
A0
A1 A2
U0
WP
* D0 to D17 : 512M bits DDR2 SDRAM U0 : 2k bits EEPROM Rs1 : 22 Rs2 : 7.5
Notes : 1. DQ wiring may be changed within a byte. 2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships must be meintained as shown. 3. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document.
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Logical Clock Net Structure
6DRAM loads R = 200 DRAM
DRAM
DRAM
DIMM connector
R = 200
DRAM
DRAM
DRAM
R = 200
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol VT VDD IOS PD TC Tstg Value -0.5 to +2.3 -0.5 to +2.3 50 8 0 to +95 -55 to +100 Unit V V mA W C C 1, 2 1 1 Notes 1
Notes: 1. DDR2 SDRAM component specification. 2. Supporting 0C to +85C and being able to extend to +95C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9s) and higher temperature self-refresh entry via the control of EMRS (2) bit A7 is required. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Operating Conditions (TC = 0C to +85C) (DDR2 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ VSS VDDSPD Input reference voltage Termination voltage DC input logic high DC input low AC input logic high -6E -5C AC input low -6E -5C VREF VTT VIH (DC) VIL (DC) VIH (AC) VIH (AC) VIL (AC) VIL (AC) min. 1.7 0 1.7 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 VREF + 0.200 VREF + 0.250 typ. 1.8 0 -- max. 1.9 0 3.6 Unit V V V V V V V V V V V 1, 2 3 Notes 4
0.50 x VDDQ 0.51 x VDDQ VREF VREF + 0.04 VDDQ + 0.3 VREF - 0.125 VREF - 0.200 VREF - 0.250
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ must be equal to VDD .
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
DC Characteristics 1 (TC = 0C to +85C, VDD = 1.8V 0.1V, VSS = 0V)
Parameter Symbol Grade -6E -5C -6E -5C -6E -5C -6E -5C max. 1125 1080 1665 1575 1260 1215 1800 1710 Unit mA Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1
Operating current IDD0 (ACT-PRE) (Another rank is in IDD2P) Operating current IDD0 (ACT-PRE) (Another rank is in IDD3N) Operating current IDD1 (ACT-READ-PRE) (Another rank is in IDD2P) Operating current IDD1 (ACT-READ-PRE) (Another rank is in IDD3N)
mA
mA
mA
Precharge power-down standby current
IDD2P
-6E -5C
180 180
mA
Precharge quiet standby current
IDD2Q
-6E -5C
450 450
mA
Idle standby current
IDD2N
-6E -5C
630 540
mA
IDD3P-F Active power-down standby current IDD3P-S
-6E -5C -6E -5C
720 720 450 450
mA
mA
Active standby current
IDD3N
-6E -5C
1260 1170
mA
all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating current (Burst read operating) (Another rank is in IDD2P) Operating current (Burst read operating) (Another rank is in IDD3N) Operating current (Burst write operating) (Another rank is in IDD2P) Operating current (Burst write operating) (Another rank is in IDD3N)
IDD4R
-6E -5C -6E -5C -6E -5C -6E -5C -6E -5C -6E -5C
2160 1800 2700 2295 2070 1800 2610 2295 2520 2340 3060 2835
mA
IDD4R
mA
IDD4W
mA
IDD4W
mA
Auto-refresh current IDD5 (Another rank is in IDD2P) Auto-refresh current IDD5 (Another rank is in IDD3N)
mA
mA
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Parameter
Symbol
Grade
max.
Unit
Test condition Self Refresh Mode; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) -1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK (IDD); CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W;
Self-refresh current
IDD6
108
mA
Operating current IDD7 (Bank interleaving) (Another rank is in IDD2P) Operating current IDD7 (Bank interleaving) (Another rank is in IDD3N)
-6E -5C -6E -5C
2970 2970 3510 3465
mA
mA
Notes: 1. 2. 3. 4.
IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN VIL (AC) (max.) H is defined as VIN VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRAS(min.)(IDD) tRAS(max.)(IDD) tRP(IDD) tRFC(IDD) 5-5-5 5 15 60 7.5 3 45 70000 15 105 DDR2-533 4-4-4 4 15 60 7.5 3.75 45 70000 15 105 Unit tCK ns ns ns ns ns ns ns ns
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
DC Characteristics 2 (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 VTT + 0.603 VTT - 0.603 0.5 x VDDQ +13.4 -13.4 Unit A A V V V mA mA Notes VDD VIN VSS VDDQ VOUT VSS 5 5 1 3, 4, 5 2, 4, 5
Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current Output minimum source DC current IOL IOH
Notes: 1. 2. 3. 4. 5.
The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18 at TA = 25C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter AC differential input voltage AC differential cross point voltage AC differential cross point voltage Symbol VID (AC) VIX (AC) VOX (AC) min. 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 max. VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125 Unit V V V Notes 1, 2 2 3
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as /CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
VDDQ VTR
VID
VCP VSSQ
Crossing point
VIX or VOX
Differential Signal Levels*1, 2
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
ODT DC Electrical Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Deviation of VM with respect to VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) VM min. 60 120 40 -6 typ. 75 150 50 max. 90 180 60 +6 Unit % Note 1 1 1 1
Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt(eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), and VDDQ values defined in SSTL_18.
Rtt(eff) =
VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC))
Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load.
VM =
2 x VM VDDQ
- 1 x 100%
OCD Default Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Output impedance Pull-up and pull-down mismatch Output slew rate min. 12.6 0 1.5 typ. 18 max. 23.4 4 5 Unit V/ns Notes 1 1, 2 3, 4
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization.
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Pin Capacitance (TA = 25C, VDD = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance -6E -5C Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /CS, CKE, ODT CK, /CK DQ, DQS, /DQS, DM, CB min. 1.0 1.0 2.5 2.5 max. 2.0 2.0 3.5 4.0 Unit pF pF pF pF Notes 1 1 2 2
Notes: 1. Matching within 0.25pF. 2. Matching within 0.50pF.
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V, VSS, VSSQ = 0V) [DDR2 667] (DDR2 SDRAM Component Specification)
-6E Frequency (Mbps) Parameter /CAS latency Active to read or write command delay Precharge command period Active to active/auto refresh command time DQ output access time from CK, /CK DQS output access time from CK, /CK CK high-level width CK low-level width CK half period Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS DQS latching rising transitions to associated clock edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to precharge command Active to auto-precharge delay Active bank A to active bank B command period Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Symbol CL tRCD tRP tRC tAC tDQSCK tCH tCL tHP tCK tDH (base) tDS (base) tIPW tDIPW tHZ tLZ tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH (base) tIS (base) tRPRE tRPST tRAS tRAP tRRD tWR tDAL tWTR tRTP 667 min. 5 15 15 60 -450 -400 0.45 0.45 min. (tCL, tCH) 3000 175 100 0.6 0.35 tAC min. tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 275 200 0.9 0.4 45 tRCD min. 7.5 15 (tWR/tCK)+ (tRP/tCK) 7.5 7.5 max. 5 +450 +400 0.55 0.55 8000 tAC max. tAC max. 240 340 +0.25 0.6 1.1 0.6 70000 Unit tCK ns ns ns ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns ns tCK ns ns 1 5 4 5 4 Notes
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
-6E Frequency (Mbps) Parameter Exit self-refresh to a non-read command Exit self-refresh to a read command Symbol tXSNR tXSRD 667 min. tRFC + 10 200 2 2 7 - AL 3 0 0 105 tIS + tCK + tIH max. 12 12 7.8 3.9 Unit ns tCK tCK tCK tCK tCK ns ns ns s s ns 3 2, 3 Notes
Exit precharge power-down to any non-read command tXP Exit active power-down to read command Exit active power-down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay MRS command to ODT update delay Auto refresh to active/auto refresh command time Average periodic refresh interval (0C TC +85C) (+85C < TC +95C) Minimum time clocks remains ON after CKE asynchronously drops low tXARD tXARDS tCKE tOIT
tMOD
tRFC tREFI tREFI tDELAY
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V, VSS, VSSQ = 0V) [DDR2 533] (DDR2 SDRAM Component Specification)
-5C Frequency (Mbps) Parameter /CAS latency Active to read or write command delay Precharge command period Active to active/auto refresh command time DQ output access time from CK, /CK DQS output access time from CK, /CK CK high-level width CK low-level width CK half period Clock cycle time DQ and DM input hold time (differential strobe) DQ and DM input hold time (single-ended strobe) DQ and DM input setup time (differential strobe) DQ and DM input setup time (single-ended strobe) Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS DQS latching rising transitions to associated clock edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to precharge command Active to auto-precharge delay Active bank A to active bank B command period Symbol CL tRCD tRP tRC tAC tDQSCK tCH tCL tHP tCK tDH (base) tDH1 (base) tDS (base) tDS1 (base) tIPW tDIPW tHZ tLZ tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH (base) tIS (base) tRPRE tRPST tRAS tRAP tRRD 533 min. 4 15 15 60 -500 -450 0.45 0.45 min. (tCL, tCH) 3750 225 -25 100 -25 0.6 0.35 tAC min. tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 375 250 0.9 0.4 45 tRCD min. 7.5 max. 5 +500 +450 0.55 0.55 8000 tAC max. tAC max. 300 400 +0.25 0.6 1.1 0.6 70000 Unit tCK ns ns ns ps ps tCK tCK ps ps ps ps ps ps tCK tCK ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns 5 4 4 5 Notes
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
-5C Frequency (Mbps) Parameter Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self-refresh to a non-read command Exit self-refresh to a read command Exit precharge power-down to any non-read command Exit active power-down to read command Exit active power-down to read command (slow exit/low power mode) Symbol tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS 533 min. 15 (tWR/tCK)+ (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 0 0 105 max. 12 12 7.8 3.9 Unit ns tCK ns ns ns tCK tCK tCK tCK tCK ns ns ns s s ns 3 2, 3 1 Notes
CKE minimum pulse width (high and low pulse width) tCKE Output impedance test driver delay MRS command to ODT update delay Auto refresh to active/auto refresh command time Average periodic refresh interval (0C TC +85C) (+85C < TC +95C) Minimum time clocks remains ON after CKE asynchronously drops low tOIT
tMOD
tRFC tREFI tREFI tDELAY
tIS + tCK + tIH
Notes: 1. 2. 3. 4.
For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
DQS /DQS
CK /CK
tDS
tDH
tDS
tDH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
tIS
tIH
tIS
tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter ODT turn-on delay ODT turn-on -6E -5C ODT turn-on (power down mode) ODT turn-off delay ODT turn-off ODT turn-off (power down mode) ODT to power down entry latency ODT power down exit latency Symbol tAOND tAON tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min. 2 tAC(min) tAC(min) tAC(min) + 2000 2.5 tAC(min) tAC(min) + 2000 3 8 max. 2 tAC(max) + 700 tAC(max) + 1000 2tCK + tAC(max) + 1000 2.5 tAC(max) + 600 2.5tCK + tAC(max) + 1000 3 8 Unit tCK ps ps ps tCK ps ps tCK tCK 2 1 1 Notes
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
AC Input Test Conditions
Parameter Input reference voltage Input signal maximum peak to peak swing Input signal maximum slew rate Symbol VREF VSWING(max.) SLEW Value 0.5 x VDDQ 1.0 1.0 Unit V V V/ns Notes 1 1 2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC) (min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
Start of falling edge input timing
Start of rising edge input timing
VDDQ VIH (AC)(min.) VIH (DC)(min.)
VSWING(max.)
VREF VIL (DC)(max.) VIL (AC)(max.)
TF Falling slew = VIH (DC)(min.) - VIL (AC)(max.) TF
TR
Rising slew =
VSS
VIH (AC) min. - VIL (DC)(max.) TR
AC Input Test Signal Wave forms
Measurement point
DQ RT =25
VTT
Output Load
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Pin Functions
CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A13 (input pins) Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ and CB (input and output pins) Data are input to and output from these pins. DQS and /DQS (input and output pin) DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
DM (input pins) DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS. VDD (power supply pins) 1.8V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 1.8V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected.
Detailed Operation Part and Timing Waveforms
Refer to the EDE5108AGBG datasheet (E0917E).
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
Physical Outline
Unit: mm
4.00 max (DATUM -A-)
0.5 min
Component area (Front)
1 120
B 63.00 133.35 55.00
A 1.27 0.10
240
10.00
121
17.80
4.00 min
Component area (Back)
4.00
FULL R
3.00
Detail A
2.50 0.20
Detail B 1.00 4.00
0.20 0.15
(DATUM -A-)
2.50 FULL R
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0093-01
Preliminary Data Sheet E0920E10 (Ver. 1.0)
23
30.00
EBE11ED8AGWA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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EBE11ED8AGWA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0920E10 (Ver. 1.0)
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